C8051T610DB24【PDF 182/218 页】DAUGHTER BOARD T610 24QFN SOCKET

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C8051T610/1/2/3/4/5/6/7

SFR Definition 25.8. TMR2CN: Timer 2 Control

Bit

Name

Type

Reset

7

TF2H

R/W

0

6

TF2L

R/W

0

5

TF2LEN

R/W

0

4

R/W

0

3

T2SPLIT

R/W

0

2

TR2

R/W

0

1

R

0

0

T2XCLK

R/W

0

SFR Address = 0xC8; Bit-Addressable

Bit Name

Function

7

6

5

4

3

2

1

0

182

TF2H

TF2L

TF2LEN

Unused

T2SPLIT

TR2

Unused

T2XCLK

Timer 2 High Byte Overflow Flag.

Set by hardware when the Timer 2 high byte overflows from 0xFF to 0x00. In 16 bit

mode, this will occur when Timer 2 overflows from 0xFFFF to 0x0000. When the

Timer 2 interrupt is enabled, setting this bit causes the CPU to vector to the Timer 2

interrupt service routine. This bit is not automatically cleared by hardware.

Timer 2 Low Byte Overflow Flag.

Set by hardware when the Timer 2 low byte overflows from 0xFF to 0x00. TF2L will

be set when the low byte overflows regardless of the Timer 2 mode. This bit is not

automatically cleared by hardware.

Timer 2 Low Byte Interrupt Enable.

When set to 1, this bit enables Timer 2 Low Byte interrupts. If Timer 2 interrupts are

also enabled, an interrupt will be generated when the low byte of Timer 2 overflows.

Unused. Read = 0b; Write = Don’t Care

Timer 2 Split Mode Enable.

When this bit is set, Timer 2 operates as two 8-bit timers with auto-reload.

0: Timer 2 operates in 16-bit auto-reload mode.

1: Timer 2 operates as two 8-bit auto-reload timers.

Timer 2 Run Control.

Timer 2 is enabled by setting this bit to 1. In 8-bit mode, this bit enables/disables

TMR2H only; TMR2L is always enabled in split mode.

Unused. Read = 0b; Write = Don’t Care

Timer 2 External Clock Select.

This bit selects the external clock source for Timer 2. If Timer 2 is in 8-bit mode, this

bit selects the external oscillator clock source for both timer bytes. However, the

Timer 2 Clock Select bits (T2MH and T2ML in register CKCON) may still be used to

select between the external clock and the system clock for either timer.

0: Timer 2 clock is the system clock divided by 12.

1: Timer 2 clock is the external clock divided by 8 (synchronized with SYSCLK).

Rev 1.1

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